Advanced Techniques for

3-D Processing

Links:
Boise State University

College of Engineering

Funded By:
DARPA

Managed By:
SPAWAR

Webmaster:
Amy Moll

Developing technology for forming high density, low capacitance, through-wafer interconnects.

 

Text Box: Cu filled through-wafer interconnects (TWI's) with aspect ratio of 5
 

 

 

 

 

 

 

WHY 3-D INTERCONNECTS?

On-chip and off-chip interconnects can be the limiting factors dominating the performance and cost of future electronic components in high-performance integrated circuits.  Three-dimensional integration can result in shorter chip-to chip interconnects, reduced parasitic effects, faster signal processing and reduced power consumption.  Through-wafer interconnects are a critical technology for 3-D stacking of electronic chips.  3-D stacking reduces the performance bottleneck associated with traditional, inherently long 2-D chip to chip interconnects.  The small lead lengths associated with through wafer vias will increase the overall device speed, decrease power requirements and decrease analog noise and cross-talk.  In addition to making electronic chip stacking possible, through wafer interconnects allow for the stacking of more than two chips and for heterogeneous integration of chips, for example, optoelectronic devices grown on GaAs with conventional Si IC’s.

 

TWI PROCESS OVERVIEW:

Text Box: 1. Spin photoresist & pattern
Text Box: 2. Etch vias 
Text Box: 3. Remove photoresist
Text Box: 4. Blanket deposit insulator
Text Box: 5. Blanket deposit liner and seed layer 
Text Box: 6. Spin thick photoresist on both sides         7. Pattern photoresist
8. Electroplate Copper
Text Box: 10. Remove photoresist
11. Remove seed and liner in exposed areas
12. TEST
Oval:  
Oval: