Arlen Planting

S-2011 | ECE 230/230L

Instructor:   Arlen Planting
Office:   ET 227
Phone:   (208)426-4826
Office hours:   Mon/Wed/Fri, 2:30pm – 3:30pm
or by appointment
Contact Info.: by email: clarenceplanting@boisestate.edu

COURSE INFORMATION:

Course Syllabus: pdf

Credit Hours: 3 (ECE 230), 1(ECE 230L)

Prerequisites: COMPSCI 117 or COMPSCI 125

Description (from catalog):
Number systems, Boolean algebra, logic gates, Karnaugh mapping, combinatorial circuits, flip-flops, registers, counters, sequential state-machines. Construction of small design projects.

Homework

Homework Guidelines: (pdf)

Hwk 1 (Due: Beginning of Class 01/26/2011): (pdf)

Hwk 2 (Due: Beginning of Class 02/02/2011)

  • Problems: 2.6, 2.7, 2.9, 2.13, 2.14, 2.31
  • Hint for problem 2.14 (use property 13b with 2nd sum term)

Hwk 3 (Due: Beginning of Class 02/09/2011)

  • Problems: 2.10, 2.22, 2.24, 2.25, 2.37, 2.41, 4.1, 4.2, 4,3, 4.4

Hwk 4 (Due: Beginning of Class 02/16/2011)

  • Problems: 4.6, 4.12, 4.13, 4.18, 4.19

Hwk 5 (Due: Beginning of Class 02/25/2011)

  • Problems: 5.1, 5.2, 5.3, 5.4

Hwk 6 (Due: Beginning of Class 03/04/2011)

  • Problems: 5.6, 5.8, 5.9, 5.10

Hwk 7 (Due: Beginning of Class 03/09/2011)

  • Problems: 5.21

Hwk 8 (Due: Beginning of Class 03/16/2011)

  • Problems: 6.3, 6.4, 6.5, 6.6, 6.15

Hwk 9 (Due: Beginning of Class 04/06/2011)

  • Problems: 7.1, 7.3, 7.5, 7.8

Hwk 10 (Due: Beginning of Class 04/13/2011) (pdf)

Example Test Fixture: (zip)

Hwk 11 (Due: Beginning of Class 04/18/2011)

  • 1. 4-bit counter with enable and clear
  • 2.  2 digit BCD counter
  • Both problems require printed circuit design and test fixture results

Hwk 12 (Due: Beginning of Class 04/25/2011)

  • 1. Re-do Hwk 10 with one-hot encoding and D flip-flops
  • 2.  Use test fixture supplied with Hwk 10

(supply modified test fixture source and resulting wave form)

Hwk 13 (Due: Beginning of Class 05/02/2011)

  • 1.  Re-do Hwk 10 using Mealy-Type FSM with
    • a.  D flip-flops        b.  JK flip-flops
  • 2.  Using Mealy-Type FSM design a ’100′ sequence detector with
    • a.  D flip-flops        b.  JK flip-flops
  • 3.  Using Mealy-Type FSM design a ’0010′ sequence detector with
    • D flip-flops
  • 4.  Implement at least one of the circuits from Hwk 10 on the Basys2 board

Register and Decoder example (zip)

Register File example (zip)

One Hertz (frequency divider) (zip)

 

Quiz

Quiz 1 (01/24/2011): Homework #1 topics

Lecture Notes

Simple Processor Example (zip)

Lab

  • Lab Syllabus: pdf

Lab 0 (01/17/2011): Xilinx ISE Tutorial

  •   Readme: pdf
  •   Xilinx ISE 10.1 for Design Simulation and Synthesis Tutorial: pdf

Lab 1 (01/24/2011): Intro to Digital Systems Laboratory

  •   Pre-lab Files: (zip)
  •   Readme: (pdf),  Report Template (doc)

Lab 2 (01/31/2011): Putting it together

  •   Lab Files: (pdf)

Lab 3 (02/07/2011): Universal NAND

  •   Lab Files: (pdf)

Lab 4 (02/14/2011): “Bad” Logic Circuit Re-Design

  •   Lab Files: (pdf)

Lab 5 (02/21/2011): Seven Segment Display Driver

  •   Lab Files: (pdf)

Quiz 1 – (02/28/2011) (Time Assignment) (Practice Quiz)

Lab 6 (03/07/2011): Arithmetic Unit (pdf)

Lab 7 (03/14/2011): Multiplexers and Decoders

  •   Lab Files: (zip)

Lab 8 (03/21/2011): Yet Another Arithmetic Unit Lab

  •   Lab Files: (pdf)

Lab 9 (04/04/2011): Introduction to Sequential Design

  •   Lab Files: (pdf)

Lab 10 (04/11/2011): Verilog Test Benches

  •   Lab Files: (zip)

Lab 11 (04/18/2011): Sequence Detector

  •   Lab Files: (pdf)

Final (05/03/2011): To be decided

  •   Lab Files: (zip)

ET312 Class Schedule (pdf)