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Publications

Journal Articles

  1. S. Rastegar, J. Stadlbauer, T. Pandhi, L. Karriem, K. Fujimoto, K. Kramer, D. Estrada, and K. D. Cantley, “Signal-to-Noise Ratio Enhancement In Graphene-Based Passive Microelectrode Arrays,” accepted to Electroanalysis, 2019.
  2. E. Krueger, A. Chang, D. Brown, J. Eixenberger, R. Brown, S. Rastegar, K. D. Cantley, and D. Estrada, “Graphene Foam as a 3-Dimensional Platform for Myotube Growth,” ACS Biomaterials Science and Engineering, vol. 2, pp. 1234-1241, 2016.
  3. J. W. Murphy, L. Smith, J. Calkins, G. R. Kunnen, I. Mejia, K. D. Cantley, R. A. Chapman, J. Sastra-Hernandez, R. Mendoza-Perez, G. Contreres-Puente, D. R. Alee, M. A. Quevedo-Lopez, and B. E. Gnade, “Thin film cadmium telluride charged particle sensors for large area neutron detectors,” Applied Physics Letters, vol. 105, no. 112107, 2014.
  4. Subramaniam, K. D. Cantley, and E. M. Vogel, “Logic Gates and Ring Oscillators based on Ambipolar Nanocrystalline-Silicon TFTs,” Active and Passive Electronic Components, vol. 2013, no. 525017, 2013.
  5. Subramaniam, K. D. Cantley, G. Bersuker, D. Gilmer, and E. M. Vogel, “Spike-Timing-Dependent Plasticity using Biologically Realistic Action Potentials and Low-Temperature Materials,” IEEE Transactions on Nanotechnology, vol. 12, no. 3, pp. 450-459, 2013.
  6. Subramaniam, K. D. Cantley, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Low Temperature Fabrication of Spiking Soma Circuits Using Nanocrystalline-Silicon TFTs,” IEEE Transactions on Neural Networks and Learning Systems, vol. 24, no. 9, pp. 1466-1472, 2013.
  7. K. D. Cantley, A. Subramaniam, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Neural Learning Circuits Utilizing Nano-Crystalline Silicon Transistors and Memristors,” IEEE Transactions on Neural Networks and Learning Systems, vol. 23, no. 4, pp. 565-573, 2012.
  8. A. Subramaniam, K. D. Cantley, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Submicron Ambipolar Nanocrystalline Silicon Thin-Film Transistors and Inverters,” IEEE Transactions on Electron Devices, vol. 59, no. 2, pp. 359-366, 2012.
  9. P. G. Fernandes, H. J. Stiegler, M. Zhao, K. D. Cantley, B. Obradovic, R. A. Chapman, H.-C. Wen, G. Mahmud, and E. M. Vogel, “SPICE Macromodel of Silicon-on-Insulator-Field-Effect-Transistor-Based Biological Sensors,” Sensors and Actuators B, vol. 161, no. 1, pp. 163-170, 2012.
  10. B. Chakrabarti, H. Kang, B. Brennan, T. J. Park, K. D. Cantley, A. Pirkle, S. McDonnell, J. Kim, R. M. Wallace, and E. M. Vogel, “Investigation of Tunneling Current in SiO2/HfO2 gate stacks for flash memory applications,” IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4189-4195, 2011.
  11. K. D. Cantley, A. Subramaniam, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Hebbian Learning in Spiking Neural Networks with Non-crystalline Silicon TFTs and Memristive Synapses,” IEEE Transactions on Nanotechnology, vol. 10, pp. 1066-1073, 2011.
  12. K. D. Cantley, A. Subramaniam, R. R. Pratiwadi, H. C. Floresca, J. Wang, H. J. Stiegler, R. A. Chapman, M. J. Kim, and E. M. Vogel, “Hydrogenated Amorphous Silicon Nanowire Transistors with Schottky Barrier Source/Drain Junctions,” Applied Physics Letters, vol. 97, no. 14, 2010.
  13. H. S. Pal, K. D. Cantley, S. S. Ahmed, and M. S. Lundstrom, “Influence of Bandstructure and Channel Structure on the Inversion Layer Capacitance of Silicon and GaAs MOSFETs.”  IEEE Transactions on Electron Devices, vol. 55, no. 3, pp. 904-908, 2008.

Conference Proceedings

  1. S. Gandharava Dahl, R. Ivans, and K. D. Cantley, “Modeling Memristor Radiation Interaction Events and the Effect on Neuromorphic Learning Circuits,” International Conference on Neuromorphic Systems (ICONS), Knoxville, TN, July 2018.
  2. S. Gandharava Dahl and K. D. Cantley, “Behavioral Modeling of Memristor Radiation Interaction Events,” IEEE Workshop on Microelectronic Devices (WMED) Invited Contribution, Boise, ID, April 2018.
  3. R. C. Ivans, J. M. Shumaker, and K. D. Cantley, “A CMOS Synapse Design Implementing Tunable Asymmetric Spike Timing-Dependent Plasticity,” in 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, August 2017.
  4. S. Rastegar, J. Stadlbauer, K. Fujimoto, K. McLaughlin, D. Estrada, and K. D. Cantley, “Signal-to-Noise Ratio Enhancement Using Graphene- Based Passive Microelectrode Arrays,” in 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, August 2017.
  5. S. Rastegar, J. Stadlbauer, K. McLaughlin, K. Fujimoto, D. Estrada, and K. D. Cantley, “Enhanced Signal-to-Noise Ratio Using Nanomaterial-Based Passive Neural Electrodes,” in 59th Electronic Materials Conference, South Bend, IN, June 2017.
  6. K. D. Cantley, R. C. Ivans, A. Subramaniam, and E. M. Vogel, “Spatio-Temporal Pattern Recognition in Neural Circuits with Memory-Transistor-Driven Memristive Synapses,” in International Joint Conference on Neural Networks (IJCNN), Anchorage, AK, May 2017.
  7. S. Gandharava, C. A. Walker, and K. D. Cantley, “Electrical Characteristics of Nanocrystalline Silicon Resistive Memory Devices,” in Workshop on Microelectronic Devices (WMED),” Boise, ID, April 2017.
  8. J. W. Murphy, A. Eddy, G. R. Kunnen, I. Mejia, K. D. Cantley, D. R. Allee, M. A. Quevedo-Lopez, and B. E. Gnade, “Sol gel ZnO films doped with Mg and Li evaluated for charged particle detectors,” SPIE Defense, Security, and Sensing Conference, paper 8730-17, Baltimore, MD, May 2013.
  9. I. Mejia, A. L. Salas-Villasenor, J. W. Murphy, G. R. Kunnen, K. D. Cantley, D. R. Allee, B. E. Gnade, and M. A. Quevedo-Lopez, “High-performance logic circuits using solution-based, low-temperature semiconductors for flexible electronics,” SPIE Defense, Security, and Sensing Conference, paper 8730-2, Baltimore, MD, May 2013.
  10. K. D. Cantley, P. G. Fernandes, M. Zhao, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Noise Effects in Field-Effect Transistor Biological Sensor Detection Circuits,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, August 2012.
  11. A. Subramaniam, K. D. Cantley, R. A. Chapman, H. J. Stiegler, and E. M. Vogel, “Submicron Ambipolar Nanocrystalline-silicon TFTs with High-κ Gate Dielectrics,” International Semiconductor Device Research Symposium (ISDRS), College Park, MD, 2011.
  12. K. D. Cantley, A. Subramaniam, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “Spike Timing-Dependent Synaptic Plasticity Using Memristors and Nano-Crystalline Silicon TFT Memories,” in 11th International Conference on Nanotechnology (IEEE Nano), Portland, OR, August 2011. 
  13. A. Subramaniam, K. D. Cantley, R. A. Chapman, B. Chakrabarti, and E. M. Vogel, “Ambipolar Nano-crystalline-silicon TFTs with Submicron Dimensions and Reduced Threshold Voltage Shift,” in 69th Annual Device Research Conference (DRC) Digest, pp. 99-100, Santa Barbara, CA, June 2011.
  14. K. D. Cantley, A. Subramaniam, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, “SPICE Simulation of Nanoscale Non-Crystalline Silicon TFTs in Spiking Neuron Circuits,” International Midwest Symposium Circuits and Systems (MWSCAS), Seattle, WA, August 2010.
  15. K. D. Cantley, Y. Liu, H. S. Pal, T. Low, S. S. Ahmed, and M. S. Lundstrom, “Performance Analysis of III-V Materials in a Double-Gate nano-MOSFET,” IEDM Technical Digest, December 2007.
  16. M. S. Lundstrom, K. D. Cantley, and H. S. Pal, “Nanoscale Transistors:  Physics and Materials,” Materials Research Society Fall Proceedings, Volume 958, Symposium L.  Boston, MA, November 2006.

Book Chapters

  1. K. D. Cantley, A. Subramaniam, and E. M. Vogel, “Spike Timing-Dependent Plasticity Using Memristors and Nano-Crystalline Silicon TFT Memories,” Chapter 26 in Nanoelectronic Device Applications Handbook, Ed. by J. Morris and K. Iniewski: CRC Press, 2013.