Sin Ming Loo

Spring 2009

Hwk Assigned on 1/23/2009: pdf, Note: for problem 3, please refer to course textbook chapter 2, Figure 2.10 (page 28 of textbook).

Hwk assigned on 1/26/2009: 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.8, and 2.9. (see page 70-74 of textbook)
Hwk assigned on 1/28/2009: 2.10, 2.13, 2.14, 2.24, 2.25, 2.26, and 2.27. (see page 70-74 of textbook)
Hwk assigned on 1/30/2009: 2.29, 2.30, 2.31, 2.34, and 2.35. (see page 70-74 of textbook, for problems 2.31 and 2.34, convert the timing diagram to truth table where x₁ is the most significant variable, and x₃ is the least significant variable.)

Hwk for 2/2/2009 lecture: 2.36, 2.37, 2.38, and 2.39.
Hwk for 2/4/2009 lecture: 4.1, 4.2, 4.3, and 4.4.
Hwk for 2/6/2009 lecture: 4.6, 4.12, and 4.13. (4.8 is removed!)

Hwk for 2/9/2009 lecture: 4.16, 4.17, 4.19, 4.20
Hwk for 2/11/2009 lecture: 4.22, 4.33
Hwk for 2/13/2009 lecture: 4.10, 4.21
Hwk for 2/16/2009 lecture: no class today
Hwk for 2/18/2009 lecture: no formal hwk for today’s lecture
Hwk for 2/20/2009 lecture: 5.1, 5.6
Hwk for 2/23/2009 lecture: No hwk

Hwk for 2/25/2009 lecture: Test

Hwk for 2/27/2009 lecture: 5.2, 5.3, 5.4
Hwk for 3/2/2009 lecture: 5.8, 5.9, 5.10
Hwk for 3/4/2009 lecture: 5.14, 5.21, 5.22, 5.23

Hwk for 3/6/2009 lecture:
1. Design a 8-to-1 Mux using optimum number of 4-to-1 Mux(s) [4-to-1 Mux(s) only!]
2. Design a 8-to-1 Mux using optimum number of 2-to-1 Mux(s) [2-to-1 Mux(s) only!]

Hwk for 3/9/2009 lecture: 6.1, 6.2, 6.4, 6.6
Hwk for 3/11/2009 lecture: 6.11, 6.15, and in class, we worked using x, then y, then z. Redo this problem using 4-to-1 Mux and 2-to-1 Mux using variables sequence y-x-z and z-y-x.
Hwk for 3/13/2009 lecture:
1. Design a shifter. The shifter is capable of processing one 4-bit input and it has a 2-bit control input. When the control input == 00 (shift left by 1 bit), 01 (shift right by 1 bit), 10 (rotate left by 1 bit), 11 (rotate right by 1 bit).

Hwk for 3/16/2009 lecture: pdf
Hwk for 3/18/2009 lecture: 6.17, 6.23, Design and simulate (Xilinx ISE 10.1i) a logic circuit that will generate a true (output a “1″) signal when A is greater or equal () to B. Otherwise, the output is zero. A and B are 4-bit unsigned numbers.
Hwk for 3/20/2009 lecture: 7.3
Week 3/23 – 3/27 — Spring Break

Hwk for 3/30/2009 lecture: 7.1, 7.5
Hwk for 4/1/2009 lecture: 7.8, Design a sequence counter with the following outputs 01 -> 10 -> 00 -> 11. After 11, it will start the count sequence again from 01. Simulate this using Xilinx ISE software (print the schematic diagram and waveform simulation). Once this is working, add a control signal (1-bit control input signal) for the sequence counter, such that it can control the direction of count sequence. You also need to simulate this using the Xilinx ISE software.
Hwk for 4/3/2009 lecture: no hwk for today’s lecture

Hwk for 4/6/2009 lecture: Test 2
Hwk for 4/8/2009 lecture: Design and simulate a 3-bit up/down counter
Hwk for 4/10/2009 lecture: Design and simulate a sequence detector that detects sequence “10″. Overlapping sequence is allowed.

Hwk for 4/13/2009 lecture: Re-design the 3-bit up/down counter (hwk for 4/8)using one-hot encoding. Simulation is optional for this hwk.
Hwk for 4/15/2009 lecture: 8.3, 8.11
Hwk for 4/17/2009 lecture: 8.21, 8.24, 8.26

Hwk for 4/20/2009 lecture: no formal hwk, but you need to know the structure of inverter, NAND, AND, NOR, and OR gates in NMOS and PMOS.
Hwk for 4/22/2009 lecture: 8.29, re-solve 8.3 using JK flip-flops with minimized bit encoding, and re-solve 8.11 using one-hot encoding and D flip-flops.
Hwk for 4/24/2009 lecture: No hwk for today’s lecture, you need to read example 8.6 for Monday’s lecture!