EE 230L – Digital Systems Lab
Fall 2006
Lab 0 (Week 1):
Xilinx ISE 8.1i for Design Simulation and Synthesis Tutorial (pdf, html)
Laboratory Completion Checklist (pdf)
Lab 1 (Week 2):
Instruction (pdf), Blank Basic Gates Summary (pdf), Report Template (doc),
Gates Data Sheet (zip), Peer Rating Form (pdf), Protoboard Diagram (pdf)
Lab 2 (Week 3):
Instruction (pdf)
Lab 3 (Week 4):
Instruction (pdf)
Lab 4 (Week 5):
Instruction (pdf), FPGA Programming Instructions (pdf)
Lab Test (Week 6):
Lab 5 (Week 7):
Instruction (pdf)
Lab 6 (Week 8):
Instruction (pdf), Seven-Segment Sequence Driver (sssd.zip) (This is a zip file, extract sssd.vhd from this zip file. This webserver doesn’t allow me to link filenme.vhd directly! Add this file to your project, then create a symbol.)
Lab 7 (Week 8):
Instruction (pdf)
Lab 8 (Week 9):
Test equipment
Lab 9 (Week 10):
Instruction (pdf)
Lab 10 (Week 11):
Implement Problem #4 of Test 2 [Design a logic circuit to convert 4-bit binary number (range 0 to F) to BCD (range 0 to 9) representation. Show how the BCD representation can be displayed to two seven-segment LEDs.]
Lab 11 (Week 12) [last lab!]:
Instruction (pdf)
Project: (pdf)